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A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1),...
To enhance RF performance, low-k/Cu dual-damascene (DD) contact is implemented into 40 nm-node CMOS devices for the first time. The Cu DD contact in reliable double-layered low-k films of silica-carbon composite (SCC, k=3.1) and SiOCH (k=3.1) boosts the cut-off frequency (fT) and the maximum oscillation frequency (fmax) by 8.0 % and 10.5% referred to those of the conventional SiO2/W-plug structure,...
A new direct low-k/Cu dual damascene (DD) contact line has been developed for low loss (low parasitic capacitance and low resistance) CMOS device platforms by on-current BEOL technologies. The excellent low contact resistance is realized in the low-k pre-metal-dielectrics (PMD) with a reduced aspect ratio, achieving 5.4 Omega for 75 nmphi contact which is only 1/4 relative to a conventional W-plug...
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