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An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device,...
Bandgap-tunable SiON (oxynitride) tunnel barrier is developed to optimize the performance and reliability of BE-SONOS NAND Flash devices. The HTO O2 layer of the ONO tunnel barrier is replaced by SiON thin films with various refractive index (n) and thickness. We found that with n ≤ 1.72, SiON can provide excellent data retention comparable to conventional BE-SONOS. On the other hand, the erase speed...
The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
Sub-30 nm TFT CT NAND flash devices have been extensively studied. Although TFT devices were often believed to have much worse performance than bulk devices, our results show that as devices scale down to sub-30 nm, the DC characteristics (such as read current and subthreshold slope (S.S.)) approach those of the bulk devices because sub-30 nm TFT devices often contain no grain boundaries. The memory...
The present study investigates the charge trapping characteristics of Si-rich nitride thin films in detail by using the gate-sensing and channel-sensing (GSCS) method. Analytical results indicate that thicker (>7 nm) nitride thin films are fully-capturing; the trapped electrons are distributed in the center of the nitride, and the charge centroid is independent of the N/Si ratio. However, thinner...
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