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Lithographic process variations, such as changes in focus, exposure, resist thickness introduce distortions to line shapes on a wafer. Large distortions may lead to line open and bridge faults and the locations of such defects vary with lithographic process corner. Based on lithographic simulation, it is easily verified that for a given layout, changing one or more of the process parameters shifts...
Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridges. This paper presents a fast and accurate technique to model the effect of process variation on resistive bridge defects. The proposed model is...
In nanometer ICs, when several transistors in physical proximity switch within the same clock cycle, a substantial power supply drop, known as droop, may occur because of concurrent load on a via of the power grid. Transistors may slow down because of lower supply voltage. Modelling of such timing faults, termed as droop faults, and their impact on the functionality and timing behaviour of the circuit...
The length of poly-gate printed on silicon depends on exposure dose, depth of focus, photo-resist thickness and planarity of the surface. In sub-wavelength lithography, polygate length also varies with layout topology. Poly-gate length determines the effective channel length of a transistor, which determines its performance. Since the sources of error are hard to control, statistical analysis can...
Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as major challenges in ITRS. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variation in sense amplifiers lead to significant loss of yield. In this paper, we present a process variation tolerant self-compensating...
Photolithography is at the heart of semiconductor manufacturing process. To support continued scaling of transistors, lithographic resolution must continue to improve. At today's volume manufacturing process, a light source of 193 nm wavelength is used to print devices with 45 nm feature size. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used...
Sub-wavelength lithography causes the shape of transistors to differ from idealized rectangles. Several researchers have proposed transistor simulation models to characterize the non-ideal shapes of transistors for various regions of transistor operation. It has been shown that the effective channel length of a non-rectangular gate (NRG) transistor may be different for ON and OFF currents. In this...
Aggressive scaling of CMOS transistors in last four decades has resulted in circuits with progressively higher packing density, increased switching speed, and higher power density. However in future, CMOS technology nodes are predicted to suffer from greater intermediate to long-term reliability and circuit marginality problems. To address these problems researchers have proposed the usage of redundant...
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