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With increasing number of cores in a SoC, the number of on-chip sensors to monitor temperature, voltage and soft errors is growing. Several researchers have suggested that even in multi-core/many-core era, the power and voltage management would still remain centralized. This necessitates an efficient channel to communicate sensor data towards the central control unhindered by the application data...
The actual traffic data collected on various applications specific on-chip networks exposed that the network traffic is self-similar in nature. In this work, modeling of self-similar traffic by aggregation of a large number of on-off Pareto sources has been discussed. We have developed a cycle accurate network simulator for evaluating the performance of wormhole router based network by varying locality...
Scalability has become an important consideration in Network-on-Chip (NoC) designs. The word scalability has been widely used in the parallel processing community. For massively parallel computing, a scalable system has the property that performance will increase linearly with the system size. The scalability analysis may be used to select the best architecture for a problem under different constraints...
This paper presents design-for-debug (DfD) methods for the reuse of network-on-chip (NoC) as a debug data path in an NoC-based system-on-chip (SoC). We propose on-chip core debug supporting logics which can support transaction-based debug. A debug interface unit is also presented to enable debug data transfer through an NoC between an external debugger and a core-under-debug (CUD). The proposed approach...
Conventional test access mechanism (TAM) and test wrappers of complex system-on-chip (SoC) designs do not adequately utilize the system resources available in the functional mode of operation. With the advent of network-on-chip (NoC), the internal data transaction bandwidth has risen dramatically. This increase does not automatically translate to benefits during test. In this paper, we present a core...
Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. NoC has emerged as a new paradigm for designing core based System-on-Chip (SoC). The success of NoC design relies...
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