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Double Patterning Lithography (DPL) is currently being used as part of Resolution Enhancement Technique (RET) in 45nm and 32nm technologies. DPL involves partitioning a layout into two masks to reduce interference from neighboring patterns and improve resolution. Triple pattern lithography has also been suggested as a way to continue scaling with trailing lithography technology. However, due to complexity...
Stringent design rules and RET (resolution enhancement technique) measures prevent occurrence of interconnect opens and shorts. However, success of this strategy depends on completeness of physical design rules. In deep sub-wavelength lithography, all physical design rules or their context sensitivity to reticle position may not be fully understood a priori. As a result defects may arise in silicon...
For process nodes 22nm and below, a multitude of new manufacturing solutions have been proposed to improve the yield of devices being manufactured. With these new solutions come an increasing number of defect mechanisms. There is a need to model and characterize these new defect mechanisms so that (i) ATPG patterns can be properly targeted, (ii) defects can be properly diagnosed and addressed at design...
Lithographic process variations, such as changes in focus, exposure, resist thickness introduce distortions to line shapes on a wafer. Large distortions may lead to line open and bridge faults and the locations of such defects vary with lithographic process corner. Based on lithographic simulation, it is easily verified that for a given layout, changing one or more of the process parameters shifts...
Physically unclonable functions (PUF) are designed on integrated circuits (IC) to generate unique signatures that can be used for chip authentication. PUFs primarily rely on manufacturing process variations to create distinction between chips. In this paper, we present novel PUF circuits designed to exploit inherent fluctuations in physical layout due to photolithography process. Variations arising...
Printed image on silicon wafer differs from layout due to optical diffraction. Optical proximity correction (OPC) is a layout distortion technique to improve printed image. During manufacturing, parameters such as focus, dose and resist thickness may vary within tolerance margins. These factors contribute to additional distortion of expected printed shape, not addressed directly by OPC. To ensure...
The length of poly-gate printed on silicon depends on exposure dose, depth of focus, photo-resist thickness and planarity of the surface. In sub-wavelength lithography, polygate length also varies with layout topology. Poly-gate length determines the effective channel length of a transistor, which determines its performance. Since the sources of error are hard to control, statistical analysis can...
Optical lithography is an indispensible step in the process flow of design for manufacturability (DFM). Optical lithography simulation is a compute intensive task and simulation performance, or lack thereof can be a determining factor in time to market. Thus, the efficiency of lithography simulation is of paramount importance. Coherent decomposition is a popular simulation technique for aerial imaging...
Lithographic variability and its impact on printability is a major concern in today's semiconductor manufacturing process. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used. While RET techniques allow printing of sub-wavelength features, the feature width itself becomes highly sensitive to process parameters, which in turn detracts from yield...
Photolithography is at the heart of semiconductor manufacturing process. To support continued scaling of transistors, lithographic resolution must continue to improve. At today's volume manufacturing process, a light source of 193 nm wavelength is used to print devices with 45 nm feature size. To address sub-wavelength printability, a number of resolution enhancement techniques (RET) have been used...
Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology. However, in recent times the wavelength of the optical light source used for photolithography has not scaled in the same rate as that of the minimum feature size of the transistor. In fact, starting with 180 nm devices, the wavelength of optical source has remained the same (at...
As the VLSI technology marches beyond 65 and 45 nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wavelength lithography, the shape of the transistor often differs from idealized rectangles. In silicon, the effective channel length of a transistor varies across its width. This is a modeling problem. The average effective...
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