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In this research, a new structure and process integration for backside illuminated CMOS image sensor by using thin wafer handling technology is proposed. First of all, the wafer of CMOS image sensor is temporarily bonded to a silicon carrier wafer with thermal plastic material and ZoneBond technology. Then the CMOS wafer is thinned down to few microns to detect the light from the backside. After thinning...
In this study, a wafer-level 3D integration scheme with Cu TSVs based on Cu/Sn micro-bump and BCB adhesive hybrid bonding is demonstrated. To realize the signal transmission effects in high speed digital signaling via Cu TSV and Cu/Sn micro-joint interconnection, the insertion loss was investigated by simulation analysis with variable TSV pitches, micro-bump diameters and chip thicknesses. Key technologies...
A wafer-level 3D integration structure with Cu TSVs based on Cu/Sn micro-bumps and BCB hybrid bonding is demonstrated. Kelvin structure and daisy chain design are adopted for electrical characterization and reliability evaluation. The results indicate the developed 3D integration scheme has excellent reliability and electrical stability.
This paper summarizes and reports systematical studies of Cu-based bonding technology for 3D IC applications. Hybrid Cu-oxide and Cu-polymer bonding designs and schemes are investigated. Electrical performances and reliability of Cu bond structures provide important guidelines for future 3D IC applications.
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