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Redundancy removal, i.e., identifying and eliminating redundant logic, is an essential optimization strategy for decreasing design area, reducing critical path delay, and simplifying circuit testability analysis. However, redundancy removal strategies invoke time-consuming proof engines with worst-case exponential behavior. While continual enhancements to heuristics resident in these engines result...
With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review...
Coupling effect due to line-to-line capacitance is of serious concern in timing analysis of circuits in ultra deep submicrometer CMOS technology. Often coupling delay is heavily dependent on temporal correlation of signal switching in relevant wires. Temporal decorrelation by shifting timing window can alleviate performance degradation induced by tight coupling. This paper presents an algorithm for...
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