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In0.53Ga0.47As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In0.53Ga0.47As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS∼95 mV/dec., Ion/Ioff ∼105, DIBL ∼51 mV/V at Vds = 0.5V for Lg=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high...
A novel multilayer dual-mode filter based on substrate integrated hexagonal cavity (SIHC) that supports two degenerated modes is demonstrated. The proposed filter is composed of a modified extended-doublet. By profit from two coupled dual-mode hexagonal cavity and asymmetry feeding structure, three transmission zeros (TZs) are generated. Accordingly, the filter not only has good selectivity due to...
A novel multilayer dual-mode filter based on substrate integrated hexagonal cavity (SIHC) that supports two degenerated modes is demonstrated. The proposed filter is composed of a modified extended-doublet. By profit from two coupled dual-mode hexagonal cavity and asymmetry feeding structure, three transmission zeros (TZs) are generated. Accordingly, the filter not only has good selectivity due to...
Solar cells embedded in the SOI substrate were successfully used as the sole energy source to power a ring oscillator fabricated using an ultra-low-power fully depleted SOI process on the same wafer. The speed of the ring oscillator increased with increasing light intensity and showed a fastest oscillation with a 4.5 ns stage delay and 0.26 fJ power-delay product. The maximum power generated by the...
We have characterized the dependence of residual strain/stress on annealing process (post- and in-situ annealing) in single-layer FePt films prepared by sputtering onto amorphous glass substrates. A remarkable difference of evolutions in residual strains between post-andin-situ annealed samples was observed by method using synchrotron radiation. The onset of ordering temperature...
As electronic devices become lighter, thinner, shorter, and smaller, IC packages follow. Low-profile type packages are reduced in thickness, so the stiffness of thin type packages is weaker due to the thermo-mechanical effects of manufacturing processes, testing, and operations. Due to the different temperatures in those processes, and the differences in coefficient thermal expansion (CTE) of each...
This paper presents a batch microfabrication approach for processing silicon-on-insulator (SOI) wafers to selectively miniaturize device features to sub-micrometers in thickness. The process was demonstrated to construct gripping devices, reducing the thickness of the gripping tips to 1 ??m while maintaining a 25 ??m thickness for all other structural components. Post processing steps were applied...
To eliminate the process of stacked with wire bonding interconnection technology, a through via silicon interposer which is used in stacked dies flip chip are assembled in this study currently. In this study, stack assembly process sequence and the sequence effect on solder joints formation 2nd level joints (between interposer chip and substrate) will be presented. 2nd level joints will be compared...
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