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There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently...
Test patterns of path delay faults (PDFs) are usually generated with static or robust sensitizing criteria for side inputs of gates, because defects affecting the delays of the PDFs will be captured by these patterns unconditionally. However, under functional sensitization (FS), there exist a class of defects that can be tested unconditionally, if they are not masked by the off-input controlling values...
With continuing trends to embed more on-chip test circuits, increasing complexity requires more efforts on design and validation. In this paper, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. In our experiments, 30% to 50% total costs are saved compared...
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