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We present the design and test results for D-band CMOS transmitter (Tx) and receiver (Rx) for ultra-high speed and short distance data communications. The Tx/Rx employs modulation/de-modulation based on Amplitude-Shift Keying (ASK) to facilitate a non-coherent data link without power-hungry PLL, data converters, and complex DSP. The Tx consists of a wideband 131~140GHz VCO along with an On/Off key...
A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting a 802.15.3c heterodyne TRX is reported. The PLL can generate 6 equally spaced tones from 43.2GHz to 51.84GHz, which is suitable for a heterodyne architecture with LO=(4/5)RF. Phase noise is measured directly at the LO frequency and is better than -97.5dBc/Hz@1MHz across the entire band. The total power consumption is...
In this paper, a novel circuit topology of CMOS divide-by-three injection-locked frequency divider is demonstrated. By using a differential direct injection pair with a LC-tank oscillator, the proposed circuit can perform the division ratio of three while the wide locking range is obtained. Based on the presented circuit architecture, a V-band frequency divider is implemented in 65-nm CMOS for demonstration...
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