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Excellent scalability of a novel CuxSiyO emRRAM down to 22 nm node is demonstrated based on statistical data of 1 Mb test chip for the first time. The integration utilizes the standard logic process and the RRAM size is shrunk by spacer pattern technology. The reset current decreases by 5X from 130nm to 22nm node with maintaining robust data retention (10yrs. @150°C), good resistance distribution...
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