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This paper described the design and implementation procedure of Transmission Control Protocol (TCP) hardwiring and TCP offloading engine based on Field Programmable Gate Array (FPGA). The design consists of several modules, and the connection among modules is implemented by buses. The result shows that some functions are realized in this design. The most contribution of this paper is that the design...
In this paper, we mainly study the key technical issues of Network-on-Chip (NoC), focusing on the analysis of typical NoC mapping problems, and making further research on the fault-aware NoC task mapping. Firstly, we study some critical problems in the design of NoC task mapping, then summarized a fault model, and finally, verified the related issues of NoC on verification platform and Field Programmable...
Aiming at the reduction of the effects of single event upsets (SEUs) which must be considered in Space applications of Field Programmable Gate Array (FPGA), a novel dependable dual module redundancy (DMR) system based on dynamic configurable FPGAs is presented in this paper. The system can not only detect faults but also recovery the circuits effectively. Using dynamic reconfigurable methodology,...
This paper describes the design flow of Secure Hash Algorithm (SHA-1) which based on LEON2 coprocessor, and provides a series of optimized design proposals. First, modify the interface of the coprocessor to increase the bandwidth; second, make use of the principle of data-driven to expand the instruction set; next, through optimizing the critical path design, dynamic generating the variables Wt (0lestles79)...
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