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In this paper, a 13-bit serial to parallel GaAs digital circuit based on GaAs 0.15um Enhancement-Depletion(ED) PHEMT has been realized and measured. This serial to parallel circuit is designed for the 6–18 GHz T/R module, it controls 1-bit switch, 6-bit shifter and 6-bit attenuator. This GaAs logic circuit could reduce the size of T/R module chip and improve the integration degree of the system. The...
This paper presents a G-band balanced tripler using 0.1 um GaAs process. An anti-parallel diode pair (APDP) structure is applied in the tripler to obtain the third harmonic signal. The balanced architecture with two 90° Lange couplers is employed for doubling the output power, improving input and output impedance matching, as well as increasing the spurious suppression. The measurement results show...
This paper presents a 40–50 GHz low insertion loss 6-bit digital step attenuators. The attenuator has a maximum attenuation range of 31.5 dB with 0.5 dB steps (64 states). It is the first full 6-bit digital attenuator reported over the frequency range of 40–50 GHz to the best of the authors' knowledge. An accurate field effect transistor's (FET's) switch model is developed, which is crucial for the...
This paper presents a new design approach for wideband spiral transformer balun in GaAs process. By using even and odd mode method, analytical solution for ideal amplitude and phase balance conditions are derived. A first order equivalent circuit of transformer is employed to illustrate the approach utilizing the parasitic capacitances of transformer at high frequency for balun design. Based on this...
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