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In ultrasound image analysis, the speckle tracking methods are widely applied to study the elasticity of body tissue. However, “feature-motion decorrelation” still remains as a challenge for the speckle tracking methods. Recently, a coupled filtering method and an affine warping method were proposed to accurately estimate strain values, when the tissue deformation is large. The major drawback of these...
In ultrasound image analysis, speckle tracking methods are widely applied to study the elasticity of body tissue. However, “feature-motion decorrelation” still remains as a challenge for speckle tracking methods. Recently, a coupled filtering method was proposed to accurately estimate strain values when the tissue deformation is large. The major drawback of the new method is its high computational...
With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual content understanding and classification. To improve the performance and energy-efficiency of the computation-demanding CNN, the FPGA-based acceleration emerges as one of the most attractive alternatives. In this paper we design and implement...
Based on the research of CABAC arithmetic and the decoding flow, the paper indicates the bottleneck in CABAC decoding process and presents a novel architecture of CABAC decoder which takes optimization design for main function modules. Detail design for its architecture and function modules is described in the paper. Simulation and FPGA verification are implemented, and the results show that the decoder...
This paper presents the IP core design of PLC (programmable logic controller) microprocessor that includes a special Boolean process unit after analysing PLC programming language, instruction execution characteristics and current PLC disadvantage. The novel microprocessor based on RISC architecture for PLC accords with PLCs international standard and its systematic design requirement. It is successfully...
A discrete wavelet packet transform hardware design based on frame-partitioned architecture is presented in this paper. In the design of the processor, a kind of optimization technique of memory-the same address operation is proposed, which can decrease the size of the memory and raise the hardware utility efficiency. A two-buffer structure memory system is evolved to meet the real time request of...
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