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Vertical topologies of on-chip silicon miniature multispiral stacked inductors are addressed, which have been fabricated by a 0.18-mum CMOS process. A generalized topological circuit model is first developed with mutual capacitive and inductive couplings treated appropriately. A set of analytical equations is given for calculating all mutual frequency-independent (dc) inductances among different spirals...
A compact circuit model for predicting performance parameters of multi-layer inductors is proposed in this paper. This model, which does not use any fitting and optimized parameters, modeled eddy currents loss in the silicon substrate, skin and proximity effects in metal tracks, which is combined with partial element equivalent circuit (PEEC) method. Excellent agreements are obtained between the modeled...
This paper presents a wideband circuit model of silicon-based interconnects for predicting their metallic and silicon substrate losses at higher frequencies. The skin and proximity effects in the structure are characterized using the partial element equivalent circuit (PEEC) method, and the parasitic parameters in silicon substrate are captured according to some analytical equations. Good agreements...
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