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This paper explores the capability of FPGA solutions to accelerate scientific applications with variable-precision floating-point (VP) arithmetic. First, we present a special-purpose Very Large Instruction Word (VLIW) architecture for VP arithmetic (VV-Processor) on FPGA, which uses unified hardware structure to implement various VP algebraic and transcendental functions. We take exponential and trigonometric...
This paper aimed to improve MIMO detector's performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4 × 4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes...
In this paper, we propose a wireless sensor network (WSN) whose behavior can be dynamically customized by injecting programs or roles specified by the user. To enable easy specification of the roles, a role-generation mechanism is also proposed. To realize the WSN, we introduce a reconfigurable wireless sensor node that has an ultra-low-power field-programmable gate array (FPGA) as well as a low-power...
The multiple-input-multiple-output (MIMO) technique is widely used in modern wireless communication systems because it greatly increases system capacity and improves communication reliability. However, MIMO detection is a challenging task. Sphere detection algorithms are preferred in practice as these can achieve bit error rate performances close to that of the maximum likelihood algorithm. Sphere...
A sensor node often uses a low-performance microcontroller unit (MCU) to reduce its power consumption. However, it is difficult to handle heavy tasks with the MCU. To solve this problem, we developed a new sensor node that uses an ultra-low power field-programmable gate array (FPGA) in addition to an MCU. By assigning heavy tasks, such as sensor and data processing, to the FPGA, we can avoid overloading...
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