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A 10-bit 2GS/s time-interleaved SAR ADC with low-complexity background timing skew calibration is presented. 10% of the area is utilized for the interleaving mismatch estimation and correction. The ADC achieves −64dB mismatch spur and 50.1dB SNDR at Nyquist rate, with 10.4mW power consumption and 0.014mm2 area in 16nm.
Deploying cache has been generally adopted by Internet service providers (ISPs) to mitigate P2P traffic in recent years. Most traditional caching algorithms are designed for locality-unaware P2P networks, which mainly consider the requested frequency of contents as the principle of caching policies. However, in more prevalent locality-aware conditions with biased neighbor-selection policies, the existing...
A 14-bit 100-MS/s pipelined ADC in 0.18 mum 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/-0.18 LSB and an INL of +1.1/-0.6 LSB. It achieves...
This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long...
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