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An analog, Gilbert-like CMOS multiplier, based on a novel linear current divider, is described. The divider uses a cascade of two differential pairs to produce a linear dependence between the tail current and the two output currents. A numerical algorithm has been implemented to find the optimum sizing of the active devices in order to compensate for the deviation from the ideal MOSFET square law...
This paper concerns an analog CMOS multiplier based on a novel approach to compensate for non idealities of the MOSFET square law approximation. A numerical algorithm has been implemented to find the optimum sizing of the active devices, starting from the process characteristics. The effectiveness of the proposed configuration has been demonstrated by means of electrical simulations performed on a...
A second-order, single-ended, fully integrated low- pass filter with cut-off frequency tunable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology, combining Gm values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The circuit has been designed and fabricated using 3.3-V 0.35-mum CMOS devices...
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