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The performance of logic function could be affected significantly by the noise effect as the dimension of CMOS devices scales to nanometers. Thus, many pertinent researches about noise-tolerant logic gate have received growing attention. Considering the randomness as the noise's nature, probabilistic-based approach proves better noise-immunity and three design schemes with the technique of Markov...
Multi-stage latency adders based on different prediction schemes have been proved promising to enhance the circuit performance with negligible overhead. This paper presents a novel predictor exploiting both the detection and the sequence-dependence between the successive calculations. The detection of carry-kill pattern of the input data can lower the probability of the operation with multiple clock...
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