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A CMOS 80-400 MHz 5TH order Chebyshev Gm-C low-pass filter with a unique auto tuning system is presented. The filter was designed and fabricated with TSMC 0.13-μm RF CMOS process. Experimental results show that the cut-off frequency of the filter can be tuned between 80-400 MHz, with a tuning step less than 7MHz and an average tuning error of 3.6%. The filter also realizes gain of 0-30 dB, IIP3 of...
This paper presents a 12-bit 50-MS/s pipelined Analog-to-Digital Converter (ADC) in a 65-nm 1P7M CMOS process. A hybrid architecture is selected to make a trade-off between the power dissipation and performance of the ADC. For subsampling application, a wideband Sample and Hold Circuit (SHC) is proposed, including a high-linearity input switch and a two-stage operational amplifier (opamp) with hybrid...
In this paper, an ultra-wideband low-noise-amplifier (LNA) is designed for low-voltage and multi-standard applications in 0.13 μm CMOS technology. Based on conversional resistive-negative-feedback structure, a novel feedback inductor technology is proposed. The presented LNA achieves a voltage gain of 14.7 dB, 2.95-4.1 dB noise figure from 0.5-10.6 GHz including test buffer. And the IIP3 is -7.2dBm...
An integrated 6.2-9.5GHz CMOS UWB receiver for WiMedia MB-OFDM is proposed. The fully differential receiver consists of a wideband LNA and a down conversion mixer with high and low gain mode. A low-pass filter and a programmable gain amplifier are also included. The chip was fabricated in TSMC 0.13-μm RF CMOS process. Measurement results show that the receiver achieves voltage gain from 21dB to 63dB...
This paper presents a 1.2V CMOS RSSI based on successive detection structure. An equation estimating the maximum nonlinear error is derived and the simulation results show it is more accurate than the former one proposed by P. C. Huang. The RSSI achieves a wide bandwidth from 1MHz to 500MHz. The linear dynamic range is at least 80dB. The nonlinear error based on single frequency curve fitting is within...
An integrated ultra-wideband CMOS RF front-end for UWB 6-9 GHz application is presented in this paper. A single-in-differential-out gain controllable low noise amplifier and a current-reuse bleeding IQ merged quadrature mixer are integrated as the RF front-end. This ESD protected module is implemented in TSMC 0.13μm RF CMOS process and the post-layout simulation results shows that it achieves a high...
This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs...
At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). A 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. By using the asymmetric-layout transistor, a four-stage...
This paper presents a 10-bit 40-MS/s pipelined ADC in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency...
This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits...
A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters to create the class-AB behavior in the first and second stages. With this structure, the transconductances (gm) of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved...
In this paper, a three-stage LNA employing a dual noise-matching topology has been proposed. The proposed LNA has two noise-matched CS amplifiers in the first and second stages instead of the conventional cascode configuration, and the LNA realizes lower noise figure than the conventional one. The simulation results of the proposed LNA show that an input matching and output matching result less than...
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