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As the enabling technology, virtualization plays an important role in cloud computing by providing the capability of running multiple operating systems and applications on top of the same underlying hardware. Early detection of vulnerability in virtualization is vital for virtualization performance and to protect against attacks that may lead to information leak or virtual machine(VM) escape. While...
In this paper a 32-bit multithreaded RISC microprocessor is designed and optimized to perform data moving and processing in the high-performance Network Processor which is flexible to a wide variety of networking, communications, and other data-intensive products. As a critical part of network processor, the microprocessor mainly takes in charge of Internet Protocol (IP) packets' transmitting. Forwarding...
This paper present a parallel, split bus interconnection scheme for the multi-processor system. The scheme provides a command bus and a set of data bus, each of which works independently. This bus interconnect scheme can greatly improve the bandwidth of data communication within the multi-processor system because of its characteristics of concurrency and separability.
In this paper, we propose a cost-effective way to improve the performance of DRAM based on multi-core system. A novel DRAM controller with instruction prefecthing mechanism is introduced. The controller dynamically selects Open Page(OP) or Close Page(CP) policy by getting some information of future accesses in advance. This DRAM controller with dynamic policy based on instruction prefetching(DP_BIF),...
The traditional hardware description languages (VHDL and Verilog) is not suitable for system-level modeling and Hardware Software Codesign, while the SystemC language is more suitable than the traditional HDL language for system-level modeling. This paper describes the packet processing engine(PPE) characteristics of XDNP network processor, analyze the advantage of system-level modeling in SystemC...
In this paper a multithreaded processor with hardware context switch mechanism driven by external events is presented for multi-processor system on chip (MPSoC). Combining this mechanism with asynchronous memory access the proposed processor implements Non-preemptive thread scheduling which can assure fairness of threads and optimization for single thread. The overhead of hardware thread switch is...
An integrated SDRAM controller with asynchronous access architecture is proposed. The controller takes charge of data transfer between off-chip SDRAM memory and the multicore multithreaded processors. The interleaving optimization for opposite bank is incorporated into the SDRAM controller, which can reduce memory latency and improve the memory bus performance. FPGA results show that the proposed...
A flexible and efficient ECC processor is presented in this paper. We design an application-specific instruction set for the processor. The proposed parallel architecture ECC processor provides the lowest level finite-field operations and supports arbitrary elliptic curves and various ECC algorithms over general prime filed. Based on 130 nm standard-cell technology, the processor requires 184μs for...
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