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The PA6T core is an out-of-order superscalar implementation of the power architecture. Power efficiency is achieved through micro-architecture, logic, and circuit optimizations. The processor is fabricated in a 65 nm, triple Vt, dual oxide 8 M CMOS process. Worst-case power dissipation at 2 GHz is 7 W.
This paper describes a monolithically integrated omegaz-gyroscope fabricated in a surface-micromaching technology. As functional structure, a 10 mum thick Silicon-Germanium layer is processed above a standard high voltage 0.35 mum CMOS-ASIC. Drive and Sense of the in plane double wing gyroscope is fully capacitively. Measurement of movement is also done fully capacitively in continuous-time baseband...
Integrated 10 /spl mu/m thick poly-SiGe gyroscopes are processed on top of an 8" standard 0.35 /spl mu/m CMOS wafer with 5 metal levels by using an advanced plasma-enhanced chemical vapor deposition multi-layer technology. The gyroscopes are free-moving with Q-factors for the drive mode up to 10000 at the pressure of 0.8 mTorr while the CMOS chip is fully functional.
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