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A novel high-speed single-ended D flip-flop based on a SR(set/reset)-type latch is presented in this paper. The SR-type latch is adapted to implement a dynamic stage for high-speed operation and modified to add a scan mux without setup time degradation on a data path. The proposed flip-flop enables to achieve the high-speed operation having the comparable hold time characteristics to a conventional...
This paper presents a heterogeneous configuration of two different target quad-core CPUs. To support both highperformance and high energy-efficiency depending on application requirements, two types of quad-core CPUs are implemented in one mobile application processor. The first type quad-core CPU is designed to give the highest performance at the cost of reasonable power consumption. The second type...
Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case...
This paper presents novel nonoverlapping cuspid-pulsed flip-flop, which consists of a cuspid-pulse generator and a domino-like latch. The cuspid-pulse generator supplies the domino-like latch with nonoverlapping negative and positive cuspid-shape pulses. The flip-flop allows the elimination of the second stage in the conventional semi-dynamic pulse-based flip-flops, leading to a significant reduction...
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