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With the recently proposed redundancy-based core salvaging technology, resilient processors can survive the threat of severe timing violation induced by near-threshold Vdd and function correctly at aggressive clock rates. In our observation, proactively disabling the weakest components that limit the core frequency can still maintain a higher throughput at Near Threshold Voltage (NTV) supply if the...
The traditional proportional fair scheduling algorithm can only provide users with limited fairness while the channel is changing. To solve this problem and enhance the fairness between users, an adaptive proportional fair scheduling algorithm for LTE (Long term Evolution) system is proposed. It adjusts the scheduling priority according to individual user's channel condition. The proposed algorithm...
Thread-level redundancy is an efficient approach for transient fault detection and recovery in Chip Multiprocessors (CMPs), in which two adjacent cores are statically coupled to form a functional Dual Modular Redundancy (DMR). Manufacturing process variations cause core-to-core (C2C) performance asymmetry across the chip, which can be further divided into the asymmetry among core-pairs and the asymmetry...
Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can...
Wireless sensor networks need energy-efficient mechanisms to measure topology for various aspects of network management, such as resource scheduling, performance evaluation and optimization. In this paper, we take into account the unique data aggregation communication paradigm of sensor networks: the sink node can infer the topology by exploiting whether data from various sensor nodes are received,...
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