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We demonstrate ternary CMOS (Γ-CMOS)-based standard ternary inverter (STI) for compact and power-scalable multi-valued logic (MVL) circuits. The distinguished mechanism of FG-independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/μm level which enables STI operation with ultra-low static power consumption of 7.7 pW/μm. Through...
We demonstrate a standard ternary inverter (STI) by using gate-last CMOS process with novel I–V characteristics based on off-state mechanism. Though the controllable α′ and β′ with respective design parameters, STI operation at VDD= 1 V have been investigated with static noise margin (SNM) of 210 mV.
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