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Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6 T SRAM cells. To overcome this limitation, 7 T SRAM designs were proposed...
In this paper, we present a systematic method for the designing fault tolerant reversible arithmetic circuits for finite field or Galois fields of the form GF(2m). To tackle the problem of errors in computation, we propose error detection and correction using multiple parity prediction technique based on low density parity check (LDPC) code. For error detection and correction, we need additional garbage...
In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed Monte Carlo simulations. It is observed that...
Motivated by the problem of process variation in nano-scale CMOS, in this paper, we propose a multivariate statistical technique that uses the well known approach of principal component analysis (PCA), a technique extensively used in statistical modeling, to analyse the process variations. We use this approach to extract significant statistical information from the simulated data. We also propose...
Due to high functionality integration in electronic devices and the ever increasing requirements for low power devices, there is an urgent need for novel low power approaches. The advancement in technology scaling has made it feasible to incorporate the extra functionality, however by increasing devices sensitivity to variations, the overall device yield decreases. Process and temperature variations...
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