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To meet the needs of innovative sensor network applications, sensor nodes have long evolved from underpowered single microcontroller designs into complex architectures that accommodate multiple processors and Field Programmable Gate Arrays (FPGAs). We address the problem of conceiving and implementing programs for such sensor node architectures. We rely on a universal, layered hardware/software interface...
Currently, the main components of most sensor nodes are a microcontroller and a radio. Their real-time and peak performance would be a bottleneck when executing computation-intensive tasks. Also, energy consumption may be high due to the long task-execution time. Several works [2]–[6] demonstrate that adding a coprocessor would be a solution to the problems. So far, no work have been done to analyze...
Energy consumption and real-time performance are two important metrics for wireless sensor networks (WSNs). To estimate these metrics, a number of simulation environments have been developed. However, these environments were made specifically for sensor nodes with fixed architectures. The recent generation of sensor nodes often has flexible architectures through the use of programmable hardware components,...
Hardware-software co-design techniques are very suitable to develop the next generation of sensornet applications, which have high computational demands. By making use of a low-power FPGA, the peak computational performance of a sensor node can be improved without significant degradation of the standby power dissipation. In this contribution, we present a methodology and tool to enable hardware/software...
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