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This paper reports design of a novel low-parasitic ultra-low-triggering voltage dual-directional LTdSCR ESD protection structure in foundry CMOS. It features programmable low triggering voltage of 4.7~6V, low discharging resistance of ~0.77Ω, low leakage of ~0.1nA, extremely low parasitic capacitance of ~10fF and ultra fast response of ~100ps. it achieves ESD protection of >7.8kV HBM and ~500V...
RF ESD protection circuitry design emerges as a big challenge to RF IC design, where the main problem is associated with performance degradation of RF IC due to ESD-induced parasitics. It has been difficult to incorporate the ESD impacts into RF IC design due to lack of proper co-design approach and ESD device models. This paper presents a new ESD-RFIC co-design methodology, including RF ESD design...
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