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The m-out-of-n encoded asynchronous circuits are able to implement the truly delay-insensitive circuit operations, but they suffer from higher power dissipation due to the large amount of logic cells. Besides, the throughput of the circuits is also worse than the synchronous counterparts since the four-cycle handshake protocol requires inserting a ??NULL?? token between two adjacent valid data transmissions...
This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can...
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