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In multiprocessor systems, low-latency synchronization is extremely important to effectively exploit fine-grain data parallelism and improve overall performance. This brief presents an efficient synchronization for embedded distributed multiprocessors. The proposed solution works in a completely decentralized request–response manner via explicit message exchange among the processing elements. Scalable...
This paper introduces an IP core for temperature monitoring a distributed and multi-point temperature monitoring system based on the designed IP core that has fast response time and is capable of parallel processing. Targeting temperature measuring chip DS18B20 as the control object, we implement both initialization and read/write controls of it in our IP core. The correctness of our IP core is verified...
High power dissipation due to excessive cell counts in dual-rail asynchronous circuits has been clearly recognized by researchers who are trying to overcome on-chip variation issue with this kind of delay-insensitive models. The multi-threshold-voltage power gating technique is considered as a promising solution and several studies have been made regarding its grain level. However, its application...
For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing...
To deal with unknown word and segmentation ambiguity, segmentation rules and tri-gram was used in inductive learning method. Rules were used for elementary segmentation and for better processing effectiveness in following steps. Those rules were acquired by manual labor through analyzing a tagged corpus. Inductive learning method recognized, extracted the unknown words from segmentation text recursively...
Test power is becoming a very important design consideration nowadays. In this paper, we apply power gating technique into scan-based designs for the first time to eliminate both dynamic and static power of idle logic during shift process. Different from any traditional coarse-grain or fine-grain power gating scheme, our proposal does not need to change design infrastructure and only tailors existing...
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.
This paper presents a high-throughput GCM VLSI architecture fully compliant to IEEE 802.1ae applications, which can be operated in all modes specified in the standard. Unlike previous works, with the modified parallel GHASH module, the design implements encryption efficiently without knowing the total number of data blocks in advance. Furthermore, a fully subpipelined version of loop-free key expansion...
City-bus information integrated control network is a communication network based on CAN (controller area network), provides interactive information for ECUs (Electronic Control Units) in city-bus, and accomplishes the integrated control of internal electronic and electrical devices. Because CAN specification just defines physical layer and data link layer based on ISO/OSI Reference Model, the higher...
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