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Presented is a circuit technique that mitigates the impact of single-event transient (SET) in deep submicrometer circuits with minimal speed, power, and area penalty. The technique combines a novel dual-sampling flip-flop (DSFF) and the skewed CMOS (SCMOS) circuit style. The DSFF and SCMOS are designed to eliminate SETs with the polarity of 1rarr0 and 0rarr1, respectively. We study inverter chain...
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