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Using TBD and Iwearout characterization and modeling, the influence of antifuse bitcell dimensions is evaluated. An analytical model based on silicon measurements and reliability laws allows the comparison of three bitcell architectures fabricated in standard CMOS 40nm (no extra processing). The model yields the time-to-breakdown and the wearout current as a function of the programming voltage and...
The lifetime modeling of antifuse bit cells is studied using transient measurements. Firstly, the wearout current is successfully modeled as Fowler-Nordheim. Secondly, the TDDB power-law voltage acceleration model is validated down to 30 0ns for a stress voltage of 5.5 V. Lifetime results are compared with the Multi-Vibrational Hydrogen Release Model.
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