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A novel low‐power, tuneable resolution and low‐current sensing analog‐to‐digital converter is proposed in this paper. The proposed architecture consists of silicon neurons along with digital circuits. The architecture is tuned for input signal ranging from 100 nA to 3.3 μA with power supply of 1 V/3.3 V for digital blocks and silicon neurons respectively. The design is simulated using 0.18 μm CMOS...