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Power integrity design is a critical issue in system-in-packages (SiP's). In particular, power supply disturbance excited by simultaneous switching output (SSO) noise, or core circuits is serious in a 3D stacked die packages. Therefore, decoupling schemes in such SiP's must be carefully designed to reduce the impedance of power distribution network (PDN) as low as possible up to high frequency range...
This paper discusses how to cope with dynamic power supply noise in FF timing estimation. We first review the dependence of setup and hold time on supply voltage, and point out that setup time is more sensitive to supply voltage than hold time and hold time at nominal voltage is reasonably pessimistic. We thus propose a procedure to estimate setup time and clock-to-Q delay taking into account given...
This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes...
In this paper, we propose a novel decoupling capacitance (decap) optimization technique based on simultaneous cell switching activity at the pre-layout stage. White space in the form of cell padding for the required quantity of decap is added to cells which simultaneously switch during the peak noise period, which is quickly estimated using initial timing information and the current waveforms for...
A head-disk interface (HDI) analyzer for high-density floppy disk drives (FDDs) was improved. This equipment consists of a high-shutter-speed camera and a highly sensitive image processor. It makes possible the evaluation of dynamic spacing fluctuation by analysis of interference fringe patterns on both sides of a floppy disk (FD). With this equipment, the dynamic motions of an up-head slider and...
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