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The wideband spectrum sensing is vulnerable to interferers and blockers due to inter-modulation distortion (IMD) that arises in nonlinear front-end. Traditional DSP-enhanced receivers use least mean squares (LMS) filters to mitigate IMD. We theoretically study the performance of LMS-based algorithm and give expression of its residual distortion power. We then propose a novel compensation algorithm...
A 28 nm CMOS software-defined receiver front end (SDRX) for the analog signal conditioning of high-speed data streams on cable is presented. By making efficient use of the available cable bandwidth, the presented SDRX is, to the authors' knowledge, the first reported receiver front end to enable high-speed data and Ultra-HDTV video streaming within home cable networks. This paper focuses on the SDRX...
The IEEE 802.3an standard describes full-duplex 10Gb/s Ethernet transmission over four pairs of up to 100m UTP cable. The performance required from the analog front end (AFE) of a 10GBASE-T Ethernet transceiver strongly depends on the length of the cable connected to it. Maximum-length cables require the highest performance, and hence, determine the worst-case power dissipation of the transceiver...
Two highly integrated ultra-low-power binary phase-shift keying (BPSK) receivers for short-range wireless communications are presented. The receivers consist of a power divider, two injection-locked RC oscillators with limiting buffers, and an xor output stage. The demodulation principle exploits the dynamic phase response of the two BPSK signal injected oscillators. As proofs of concept, a 300-MHz...
In this work a highly integrated, ultra-low-power BPSK receiver for short-range wireless communications is presented. The receiver consists of a power divider, two injection-locked RC oscillators with limiting buffers and an XOR output stage. The demodulation principle is based on the dynamic phase response of the two BPSK signal injected oscillators. As proof of concept, a 300 MHz receiver was implemented...
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