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Heterogeneous computing with hardware accelerators is a promising direction to overcome the power and performance walls in traditional computing systems. CPU-accelerator integrated architectures, such as CPU with ASIC or FPGA based accelerators, are able to provide customized processing according to application requirements and are thus particularly attractive to speed up computation-intensive applications...
Fine-grained runtime power management techniques could be promising solutions for power reduction. Therefore, it is essential to establish accurate power monitoring schemes to obtain dynamic power variation in a short period (i.e., tens or hundreds of clock cycles). In this paper, we leverage a decision-tree-based power modeling approach to establish finegrained hardware power monitoring on FPGA platforms...
DNNs (Deep Neural Networks) have demonstrated great success in numerous applications such as image classification, speech recognition, video analysis, etc. However, DNNs are much more computation-intensive and memory-intensive than previous shallow models. Thus, it is challenging to deploy DNNs in both large-scale data centers and real-time embedded systems. Considering performance, flexibility, and...
Heterogeneous computing is rapidly gaining increased attention due to the promise it holds in overcoming power and performance walls in traditional computing systems. With its focus on customized processing nodes dedicated to the different tasks in an application, it is hoped that these walls will be overcome. Therefore, CPU-FPGA co-architectures are also gaining ground in application areas like recognition,...
Complex Event Processing refers to different mechanisms such as event correlation and event patterns detection for processing multiple events with the goal of inferring the complicated ones. While a simple event may provide trivial information, combining several of them can help in deriving more useful information. Detecting the complex events requires huge processing capability. The existing hardware...
Dataflow graphs obtained from benchmark applications depend on the compiler used and its settings. This makes comparison of results in high level synthesis research using such dataflow graphs difficult. Therefore, a synthetic dataflow graph generator for generating dataflow graphs of any size from a few tens of nodes to thousands of nodes for research in high level synthesis is presented. The user...
In order to meet the requirements of wireless image transmission system, an interface was designed for external memory interface(EMIF) of TMS320DM365 and FPGA. Firstly, their hardware connection was given, and a stable pin is used as interrupt signal. Then the EMIF device driver under embedded Linux system was described in detail. The working process in both transmission and receiving FPGA were introduced...
This paper proposes a high speed serial data acquisition scheme. The scheme adopts Nios II soft processor in FPGA instead of application of specific chips in digital system to realize and control serial data acquisition, and especially focuses on the hardware designment with Quartus II and software development with Nios II EDS. This design shortens the design processs, simplifies the circuits, and...
A parallelized and pipelined architecture based on FPGA and a higher-level Self Reconfiguration Platform are proposed in this paper to model Generalized Laguerre-Volterra MIMO system essential in identifying the time-varying neural dynamics underlying spike activities. Our proposed design is based on the Xilinx Virtex-6 FPGA platform and the processing core can produce data samples at a speed of 1...
In this paper, a fast correction algorithm is proposed for laser marking based on SOPC(System On Programmable Chip) system. The principle of figure distortion and correction algorithm for laser marking is analyzed in detail while correction algorithm is implemented by SOPC. By taking advantage of SOPC system which supports the design of software and hardware in coordination, the embedded processor...
We present a parallelized and pipelined architecture for a generalized Laguerre-Volterra MIMO system to identify the time-varying neural dynamics underlying spike activities. The proposed architecture consists of a first stage containing a vector convolution and MAC (Multiply and Accumulation) component, a second stage containing a pre-threshold potential updating unit with an error approximation...
The advent of multiple-input-multiple-output (MIMO) techniques has resulted in the generation of new design problems, especially in the baseband processing task of symbol detection. Lattice reduction (LR)-aided detection techniques have emerged as a low-complexity method to achieve the same diversity as the maximum likelihood detector. In this article we explore efficient hardware realization of the...
Lattice reduction-aided equalization techniques have emerged as a low-complexity method to achieve the same diversity as maximum likelihood detectors. We address the VLSI implementation of these LR-aided equalizers by modifying the CLLL algorithm from a fixed-point hardware perspective. We then apply the modified algorithm together with additional micro-architecture and operation scheduling enhancements...
Spread spectrum technology can effectively solve the problems such as bad channel environment, multi-path fading etc between mobile station and subscribers. At present the research on the synchronization of PN code is more concentrated on how to implement fast acquisition. This paper introduces the sliding correlation method of PN code acquisition, gives out a serial and parallel acquisition method...
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