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An all-digital coherent-like binary frequency shift keying (BFSK) demodulation based on the use of a multi-bit shift register, two multi-bit XOR gates and a mean value filter is presented. The demodulator is fabricated in SMIC 65-nm CMOS process with a die area of 0.015mm 2 . The demodulator consumes 1.44mW with 1.2V of voltage supply and 32MHz of sample clock. The measured bit error ratio...
A novel switched-loop filter, which can significantly reduce ripples on voltage controlled oscillator (VCO) control line, is proposed for phase-locked loops (PLL) with an automatic frequency calibration technique. Complementary bootstrapped transmission gates are utilized and rearranged clocks are generated to improve the performance of loop filter. Based on the SMIC 65nm RF CMOS process, the proposed...
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