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In this letter, gate-all-around vertical nanowire (NW) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are demonstrated using a CMOS-compatible process. Both Nand P-TFT devices (with gate length down to 100 nm and a wire diameter of ~30 nm) exhibit good transistor performance, e.g., high Ion/Ioff ratio of >; 106, low subthreshold slope (SS ~ 100 mV/dec), and reasonable drain-induced...
We demonstrate excimer laser annealed dopant segregated Schottky (ELA-DSS) junction on gate-all-around (GAA) silicon nanowire pFETs. The metal-semiconductor junction interfacial doping is increased by two-fold with the ELA method. On silicon nanowire, the method achieves an effective Schottky barrier height (SBH) of nearly zero, improves the short channel performance and reduces the parasitic resistance...
A non-charge-sheet surface-potential-based compact drain-current model for long-channel undoped gate-all-around (GAA) silicon-nanowire (SiNW) MOSFETs is developed. The surface-potential equation is derived from cylindrical Poisson equation for undoped silicon and solved iteratively with a very good initial guess to reach equation residue below 10-16 V within a few iterations. The single-piece current...
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