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Leakage power is a major issue of concern in Deep Sub-Micron (DSM) and Ultra Deep Sub-micron technology (UDSM) in CMOS circuit design. LECTOR-EP (LECTOR technique with extra PMOS), LECTOR-EN (LECTOR technique with extra NMOS) and Double LECTOR techniques have been proposed in this paper to reduce the leakage. Due to increase in resistance for the path from Vdd to ground, substantial reduction in leakage...
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