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This paper presents a 12b 180 MS/s partial-interleaving Pipelined-SAR analog-to-digital converter (ADC). The 1st-stage is implemented with a 2b/cycle SAR ADC for high speed, where we propose a merged-residue-DAC technique to improve the noise performance. The capacitor pre-charging in conventional 2b/cycle operation wastes settling time and switching energy, while with this design approach the switching...
An 8-b 400-MS/s 2-b-per-cycle (2 b/C) successive approximation register (SAR) analog-to-digital converter (ADC) is fabricated in 65-nm CMOS. With the implementation of a low-power and small-area resistive DAC and associated highly integrated circuit implementation, the proposed SAR ADC achieves rapid conversion rate, low power, and compact area, leading to SNDR of 44.5 dB and SFDR of 54.0 dB, at 400...
The successive-approximation (SA) algorithm is traditionally used for low bandwidth applications because it requires n clock cycles or more to obtain n-bit resolution. However, the use of modern nanometer CMOS technologies and special design solutions overcome the speed limit, enabling conversion rates in the hundreds of MHz with very low power consumptions. This design uses the successive-approximation...
This paper proposes a differential switched-capacitor (SC) biquad filter exploiting a hybrid structure. The 1st active core is an operational amplifier (OpAmp) whereas the 2nd is an improved comparator-based circuit (CBC). The advantages of this new structure are justified by the reductions of power and transistor sizes. Optimized in a 65-nm CMOS process, when compared with a typical dual-OpAmp design,...
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