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An ultra-thinning down to 2.6-um using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness and Cu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-um within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-um while no degradation...
An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms...
An ultra-thinning down to 4-µm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-µm was approximately...
200 mm and 300 mm device wafers were successfully thinned down to less than 10 μm. A 200 nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50 nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9 μm, switching charge showed no change by the...
200-mm and 300-mm device wafers were successfully thinned down to less than 10-μm. A 200-nm non-crystalline layer remaining after the high-rate Back Grind process was partially removed down to 50-nm by Ultra Poligrind process, or was completely removed with either Chemical Mechanical Planarization or Dry Polish. For FRAM device wafers thinned down to 9-μm, switching charge showed no change by the...
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