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This paper proposed a solution for arbitrary waveform generator (AWG), in which integrated DDS chip is engaged as the essential frequency variable clock source. DACs are driven to generate the waveforms by clock signals, which are obtained from the reshaping and shape lifting of output from DDS by clock distributor. The data to build waveform up are stored in cache and loaded into DACs continuously...
This paper presents FPGA based VGA display interface design for image display verification during test procedure in the star sensor debugging phase. Methods of asynchronous FIFO, methods for data update during line blanking interval and vertical blanking interval were adopted, and CCD camera's requirements for special sequential order were satisfied, and the metastable state problem caused by data's...
This paper aims at understanding and analyzing the effects of system-on chip technology on FADEC (Full Authority Digital Engine Control) system. Now FADEC system involves three problems besides basic performances: life-cycle cost reduction, weight reduction and flexibility of system realization. The life-cycle cost is stemmed mainly from avionics obsolescence, system maintenance, advancing performances...
Pseudorandom Sequences have been widely used in many areas such as telecommunication, cryptology, navigation and radar. m-sequence is one of desirable pseudorandom sequences. By utilizing the feedback functions of m-Sequences, a new method of constructing the feedback function of the nonlinear maximal length shift registers is presented. The feedback function is constructed by using of both the characteristic...
The design scheme of hard real-time bus CANNet based on IEEE 802.3 and CAN bus is proposed for the request of multi point high broadband information interchange in the distribution intelligent control system module interconnection. The CAN arbitration mechanism is added in the physical layer of ethernet network. Thus the CANNet bus not only has Ethernet network ,but also has the property of CAN bus...
With the development of the micro-electronics and computer technology, especially with the expansion of field programmable gate array (FPGA), the reconfigurable system technology is becoming the key issue of research and application. In this paper, the principle of the dynamically reconfigurable FPGA, the method and flow of the configurable design are introduced. Based on the application requirement...
The importance of efficient area and timing estimation techniques is well-established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing HLS tools with the capability of predicting the effects of technology-specific tools on the design space. Much of the previous work has focused on estimation techniques that use very simple cost models based...
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