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The low-voltage limitations of memory-rich nano- scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip- flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI...
The low-voltage limitations of memory-rich nano-scale CMOS LSIs using bulk CMOS and fully-depleted (FD) SOI devices are described, focusing on CMOS inverter and flip-flop circuits such as six-transistor (6-T) cells in SRAMs and sense amplifiers in DRAMs. The limitations strongly depend on the ever-larger VT variation, especially in SRAM cells and logic gates, and are improved by using the FD-SOI as...
A planar double-gate FD-SOI is compared with the bulk CMOS in terms of low-voltage operations. It turns out that due to the small VT variation the FD-SOI is suitable for deep-sub-1 V operations with improved voltage margin of RAM cells and sense amplifiers, and reduced speed variations of logic gates
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