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We studied the impedance characteristics of through-silicon via (TSV)-based power delivery networks (PDNs) for hierarchical on-die simulation and interconnect noise analysis. This paper compares the quality of power delivery in 3-D stacking scenarios for three distinct chip stacking topologies: 1) face-to-back (F2B); 2) face-to-face (F2F); and 3) back-to-back (B2B). Quantitatively, this paper compared...
This paper describes an analog-to-digital converter (ADC) capable of operating in a RF-only circuit topology. A major limitation to direct RF-powered sensors are the lack of analog circuits. The proposed architecture is comprised of a cross-coupled pair of inverters, which act as the comparator for the ADC. This setup has been simulated in IBMs 0.13 µm bulk CMOS process for a 3 bit analog-to-digital...
In this study, we estimate, compare and analyze the PDN effects of four chip-stacking topologies. The chip-stacking topologies are: (1) F2B; (2) F2F; (3) B2F; and (4) B2B. The arrangement of various on-chip interconnect elements based on the chip-stacking topologies specific to the design of 3D IC-PDN, varies in impedance properties. To reduce the impedance effects NMOS decap unit cells are integrated...
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