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Mechanical failures in low- interlayer dielectrics and related interfaces during flip-chip-packaging processes have raised serious reliability concerns. The problem can be traced to interfacial fracture induced by chip–package interaction (CPI). During the packaging processes, thermal stresses arise from the mismatch in coefficient of thermal expansion between the chip and the substrate, which can...
The reliability of Cu/low k interconnect structures using Cu pillar bumps was investigated in this paper. First the characteristics related to electromigration (EM) of Cu pillars with Sn-Ag tips were studied and compared with full Pb-free Sn-Ag solder bumps. The simulation results revealed a significant reduction in the current crowding when Sn-Ag C4 solder was replaced by Cu pillar structures. As...
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