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We present a reconfigurable neural processor for real-time simulation and prediction of opto-neural behaviour. We combined a detailed Hodgkin–Huxley CA3 neuron integrated with a four-state Channelrhodopsin-2 (ChR2) model into reconfigurable silicon hardware. Our architecture consists of a Field Programmable Gated Array (FPGA) with a custom-built computing data-path, a separate data management system...
The effect of variability has become increasingly significant as a result of technology geometry scaling. This paper describes Asynchronous Assisting Logic (AAL) blocks and the method of introducing them into modern FPGA architecture, in order to increase tolerance of the wide range latency variations caused by parametric variation, and temperature and supply voltage fluctuations. The proposed method...
Dynamic clamp emerges as an important apparatus to study the intrinsic neuronal properties through close-loop interactions between models and biological neurons. Modelling large-scale neuronal networks in software will result in significant computational delay that becomes a bottleneck to apply dynamic clamp for more complicated systems. In this paper, we present a real-time dynamic clamping system...
Rapid advances in multichannel neural signal recording technologies in recent years have spawned broad applications in neuro-prostheses and neuro-rehabilitation. The dramatic increase in data bandwidth and volume associated with multichannel recording requires a significant computational effort which presents major design challenges for brain-machine interface (BMI) system in terms of power dissipation...
Parallel 1-D signal filtering algorithm is implemented as a parameterized efficient FPGA-based architecture using Xilinx System Generator. The implemented algorithm is a linear indirect filters achieved by a parallel FFT/point-by-point complex inner product/ IFFT convolution unit array. The implemented architecture manifests a 38 % higher performance per Watt at maximum frequency. The parameterized...
Currently, Field Programmable Gate Array (FPGA) goes beyond the low-level line-by-line hardware description language programming in implementing parallel multidimensional image filtering algorithms. High-level abstract hardware-oriented parallel programming method can structurally bridge this gap. This paper proposes a first step toward such a method to efficiently implement Parallel 2-D MRI image...
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