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This paper describes an energy efficient boot-strapped CMOS inverter for ultra-low power applications. The proposed design is achieved by internally boosting the gate voltage of the transistors (via the charge pumping technique), and the operating region is shifted from the sub-threshold to a higher region, enhancing performance and improving tolerance to PVT variations. Despite the proposed bootstrapped...
The current trends for greater heterogeneity in future Systems-on-Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply conditions, and associated concurrently operating modes, within an SoC calls for more efficient power delivery networks (PDN) for battery operated devices. This is especially important for systems...
This paper focusses on variability analysis for analyzing the robustness of self-timed SRAM to random process variations. The paper augments our previously proposed approaches at the circuit level which provide robustness against signals that are susceptible to deadlock with analysis techniques at the transistor level to analyze the effect of the process parameters for the transistors inside the SRAM...
A new balanced library is presented which consists of novel mixed 1-of-2 and 1-of-4 components based on -nary logic. Cryptographic circuit specifications are refined and passed to optimization and mapping tools for mapping to a library of power-balanced components. Logic optimization tools are then applied to generate secure synchronous circuits for layout generation. This paper presents a new technique...
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