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In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to...
In this work, a low-power super-regenerative receiver (SR-RX) operating in the MICS band is designed. A fast digital frequency calibration loop is proposed to adjust the oscillator center frequency to the desired frequency band and the maximum tuning time is just 2.7 μs. Some other calibration loops are also added to enhance the SR-RX performance. The SR-RX is capable of achieving a maximum data rate...
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