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This paper presents a fast and low cost on-line scheme named Charka that analyzes short faults in channels of octagon NoCs. Experimental results demonstrate that the proposed scheme achieves 100% coverage metrics and its online evaluation reveals compelling effect of these faults on system performance. We observe that the proposed scheme is upto 9X faster while packet latency is improved by 13.79–21...
With the ever shrinking dimension of a chip on a die, it is evident that the channels of on-chip networks (NoCs) are often exposed to logic level manufacturing faults such as stuck-at faults. The faults coercively put the networks into miscellaneous system level failures like packet corruption, misrouting, and dropping. Thus, the reliability has become a special interest. Additionally, the performance...
This paper proposes a cluster-based, distributed scheme for on-line testing of short faults in NoC interconnects. Proposed scheme detects both intra-and inter-interconnect short faults and identifies faulty interconnect-wires at a node. Then nodes are scheduled such that the proposed scheme offers comparative lower test time. We further see that the proposed scheduling suggests same time for larger...
The presence of open-faults in NoC channels drastically drops packets while routing them causing severe degradation of network performance. Nevertheless, it can still be compensated by utilizing a fault-repairing scheme. This paper shows how the performance of a NoC architecture can be improved through self-repairing of open channels using short-defects. Simulation results reveal that the performance...
In an on-chip network (NoC), the channels often experience several open faults because of certain manufacturing or in-field defects. Such faults may cause enormous loss of packets degrading the reliability and performance of the system. A reliability-aware NoC should include a module that has the capability of detecting and locating an open fault in the channels so as to enable alternative routing...
With the ever-shrinking global geometries on a die and the concomitant rise in the complexity of interconnections in an on-chip network (NoC), the links used therein often suffer from various manufacturing defects such as shorts. These defects not only cause logical or functional errors but also give rise to various other system level failures such as duplication, misrouting, or dropping of a packet,...
This paper presents a distributed on-line test mechanism that detects stuck-at faults (SAFs) in the channels as well as identifies the faulty channel-wires in an on-chip network (NoC). The proposed test mechanism improves yield and reliability of NoCs at the cost of few test clocks and small performance degradation. Additionally, the mechanism is scalable to large-scale NoCs. We study the impact of...
Traditional bus-based systems-on-chip (SoCs) are turned to on-chip networks (NoCs) to overcome communication bottleneck. But, fabricating such NoC-based systems without any defect in interconnects or logics is a major challenge. This paper proposes a cost effective and scalable on-line test solution that detects and diagnoses intra-and inter-shorts in NoC interconnects. The proposed solution offers...
This paper presents a scalable time optimized online test solution that addresses short faults in interconnects of an on-chip network (NoC) and observes the deep impact of these faults on NoC performance at large traffics.
Packet corruption, misrouting, and dropping have become an extra burden on network performances due to stuck-at and open faults on network-on-chip (NoC) interconnects. Existing works for testing interconnect faults have addressed either shorts and/or stuck-ats with the assumption that the opens do not exist on interconnects. A new distributed test scheme that addresses coexistent stuck-at and open...
Duplication, misrouting, and dropping of packets due to short faults on network-on-chip (NoC) interconnects have become a burden and significant impact on performance metrics. This paper proposes an adaptive approach that detects and locates intra-channel short faults on NoC interconnects, and accounts impact of the faults on performance metrics. The model is scalable with all NoCs. Simulations show...
Interconnect shorts in a network-on-chip (NoC) have caused data overloading and misrouting that make an extra burden on performance metrics. Therefore, diagnosis of shorts on NoC interconnects has taken special interest. Existing works on diagnosis of shorts on NoC interconnects have two major issues-high test time and less scalability. This paper presents a distributed packet address driven test...
Previous works on detecting and locating manufacturing faults-shorts, stuck-at, and open on an inters witch link of a channel in a network-on-chip (NoC) have been based on the assumption that these faults do not coexist. The works failed to diagnose all these faults when this assumption is relaxed. A deficiency for non-diagnosability of these faults is then represented. A packet address driven test...
With the rapid advancements of deep submicron and nano technologies the dimension of a chip is ever shrinking. With continuous shrinking of chip dimensions, immense interconnects are associated on a die to satisfy high bandwidth requirements and make a network-on-chip (NoC) architecture prone to large number of interconnect faults. Therefore the reliability becomes a crucial issue for the communicating...
Now-a-days On-line testing becomes an indispensable part of DFT (design for testability) for detecting rapidly increasing intermittent faults in deep sub-micron ICs. Much of the proposed on-line testing techniques are for synchronous circuits as compared to asynchronous circuits. The existing online testing(OLT) techniques of asynchronous circuits involve development of checkers that verify the correctness...
The network-on-chip has become an emerging research area in the fields of system on chips, embedded systems, integrated circuits design, etc. with the rapid advancement of technologies. The introduction of multi-core chips has in addition made researches in the area ever significant and is growing to facilitate high demand of bandwidth via core utilization and need of scalable interconnection fabrics...
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