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This paper presents a comprehensive analysis and comparison of hybrid MMC topologies with DC fault ride-through capability (DC-FRT), consisting of half-bridge sub-modules (HBSMs) and full-bridge sub-modules (FBSMs). Over-modulation index, semiconductor count and capacitor's capacitance with a specified rated DC voltage are mainly considered. Constraints of HBSMs' capacitors voltage balancing on over-modulation...
As VLSI technology continuously scales down, robust clock tree synthesis (CTS) has become increasingly critical in an attempt to generate a high-performance synchronous chip design. Clock skew resulted by process variations can be significantly different from the nominal value. In this paper, we propose an efficient buffer sizing algorithm to solve the skew optimization problem in presence of process...
Clock networks dissipate a significant fraction of the entire chip power budget. In contrast to most of the traditional works that handle the power optimization problem with clock routing or buffer sizing, we propose a novel register clustering methodology for power reduction of clock trees. Moreover, a fast three-stage clock tree synthesis (CTS) approach based on register clustering is presented...
Clock networks dissipate a significant fraction of the entire chip power budget. Therefore, the optimization for power consumption of clock networks has become one of the most important objectives in high performance IC designs. In contrast to most of the traditional works that handle this problem with clock routing or buffer sizing, this paper proposes a novel register clustering algorithm in generating...
Timing-driven placement has been studied for decades. Many algorithms use traditional wire-length-metric wire models and formulations to add timing driven strategies. Few works try to explore the timing potentials from the wire model of placement. Especially in the current sub-45nm era, two nets with the same wire length possibly vary distinctly from the timing property. In this paper, we explore...
As chip design complexity scales, completing routes of all nets has become a tough work under limited routing resources and increasing number of design rules. Besides, wirelength and crosstalk greatly affect the chip's performance. This paper presents a novel fine-grain track routing approach to optimize routability and crosstalk. The proposed track router is performed in a GRC-by-GRC fine-grain manner,...
For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction...
Register placement has fundamental influence to a clock network size/wirelength as a clock routing is carried out based on register locations. This paper presents a novel low-power clock placement framework which is independent of placement algorithms. Inspired by the algorithm of Divide and Conquer, the set of whole clock sinks is divided into many subsets and the optimization is mainly carried out...
Clock gating technology can reduce the consumption of clock signals' switching power of flip-flops. The clock gate enable functions can be identified by Boolean analysis of the logic inputs for all flip flops. However, the enable functions of clock gate can be further simplified, and the average number of flip flops driven by enable functions can be improved. In this way, the circuit area can be reduced;...
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